There are many commercially successful non-volatile memory products being used today, particularly in the form of small form factor cards, which use an array of flash EEPROM (Electrically Erasable and Programmable Read Only Memory) cells. Such cards may be interfaced with a host, for example, by removably inserting a card into a card slot in a host. Some of the commercially available cards are CompactFlash™ (CF) cards, MultiMedia cards (MMC), Secure Digital (SD) cards, Smart Media cards, personnel tags (P-Tag) and Memory Stick cards. Hosts include personal computers, notebook computers, personal digital assistants (PDAs), various data communication devices, digital cameras, cellular telephones, portable audio players, automobile sound systems, and similar types of equipment.
In one type of architecture, a NAND array, wherein series strings of more than two memory cells, such as 16 or 32, are connected along with one or more select transistors between individual bit lines and a reference potential to form columns of cells. Word lines extend across cells within a large number of these columns. An individual cell within a column is read and verified during programming by causing the remaining cells in the string to be turned on hard so that the current flowing through a string is dependent upon the level of charge stored in the addressed cell. An example of a NAND architecture array and its operation as part of a memory system is found in U.S. Pat. No. 6,046,935, which patent is incorporated herein in its entirety by this reference. NAND memory devices have been found to be particularly suitable for mass storage applications such as those using removable memory cards. In an alternative arrangement to the separate card and host described above, in some examples a memory system is permanently connected to a host providing an embedded memory that is dedicated to the host.
As in most integrated circuit applications, the pressure to shrink the silicon substrate area required to implement some integrated circuit function also exists with flash EEPROM systems. It is continually desired to increase the amount of digital data that can be stored in a given area of a silicon substrate, in order to increase the storage capacity of a given size memory card and other types of packages, or to both increase capacity and decrease size. One way to increase the storage density of data is to store more than one bit of data per memory cell. This is accomplished by dividing a window of a floating gate charge level voltage range into more than two states. The use of four such states allows each cell to store two bits of data, eight states stores three bits of data per cell, and so on. A multiple state flash EEPROM structure and operation is described in U.S. Pat. Nos. 5,043,940 and 5,172,338, which patents are incorporated herein by this reference.
Increased data density can also be achieved by reducing the physical size of the memory cells and/or the overall array. Shrinking the size of integrated circuits is commonly performed for all types of circuits as processing techniques improve over time to permit implementing smaller feature sizes. But there are usually limits of how far a given circuit layout can be shrunk in this manner, since there is often at least one feature that is limited as to how much it can be shrunk. When this happens, designers will turn to a new or different layout or architecture of the circuit being implemented in order to reduce the amount of silicon area required to perform its functions. The shrinking of the above-described flash EEPROM integrated circuit systems can reach such limits.
One way to form small cells is to use a self-aligned Shallow Trench Isolation (STI) technique. This uses STI structures to isolate adjacent strings of floating gate cells such as those of NAND type memory arrays. According to this technique, a gate dielectric (tunnel dielectric) layer and floating gate polysilicon layer are formed first. Next, STI structures are formed by etching the gate dielectric and floating gate polysilicon layers and the underlying substrate to form trenches. These trenches are then filled with a suitable material (such as oxide) to form STI structures. The portions of the gate dielectric and floating gate polysilicon layers between STI structures are defined by the STI structures and are therefore considered to be self-aligned to the STI structures. Typically, the STI structures have a width that is equal to the minimum feature size that can be produced with the processing technology used. STI structures are also generally spaced apart by the minimum feature size. Thus, the portions of the gate dielectric and floating gate polysilicon layers between STI regions may also have a width that is equal to the minimum feature size. The strips of floating gate polysilicon are further formed into individual floating gates in later steps.
In NAND and other types of non-volatile memories, the amount of field coupling between floating gates and the control gates passing over them (the coupling ratio) is carefully controlled. The amount of coupling determines how much of a voltage that is placed on the control gate is coupled to the underlying floating gates. The percentage coupling is determined by a number of factors including the amount of surface area of the floating gate that overlaps a surface of the control gate. It is often desired to maximize the percentage coupling between the floating and control gates by maximizing the amount of overlapping area. One approach to increasing coupling area is described by Yuan et al in U.S. Pat. No. 5,343,063, which patent is incorporated herein in its entirety by this reference. The approach described in that patent is to make the floating gates thicker than usual to provide large vertical surfaces that may be coupled with the control gates.
One problem with simply making a floating gate thicker is that the aspect ratio of STI structures formed between floating gates increases. The aspect ratio is equal to the height of the STI structure divided by its width. Thus, as the height of the floating gate increases and the height of the STI structure increases accordingly, the aspect ratio increases. Filling STI trenches that have a high aspect ratio may present certain problems. These problems are of particular concern for newer generations of memory devices that have a very small minimum feature size. The width of the STI structure in such devices may be shrunk to a very small dimension, while the depth required to electrically isolate neighboring cells remains approximately the same. Thus, the aspect ratio for such STI structures tends to be high. If the aspect ratio is too high, STI structures may not be of adequate quality. For example, voids may be formed because deposition at the opening of the STI trenches reduces deposition towards the bottom of the trenches. Such voids may cause faulty devices and contribute to yield loss.
Another problem with increasing floating gate thickness and having coupling along a vertical surface of a floating gate is that it may be difficult to accurately and uniformly control the dimensions of such surfaces. Where vertical extensions of the control gate extend downwards to provide increased coupling, the lengths of such extensions are critical. Variation in the length of such extensions may cause unacceptable variation in the coupling ratio. If the extensions are too long they may affect the channel region that underlies the gate dielectric.
A memory array is generally fabricated on a semiconductor chip with some peripheral circuits. Typically, memory arrays are made on substrates where a single substrate is later divided into separate chips with each chip having one or more memory arrays. Certain peripheral circuits may also be fabricated in a peripheral area on the same chip as a memory array. In this way, peripheral circuits may be directly connected to the memory array. Peripheral circuits may include driver circuits, sense amplifiers, charge pumps, decoder circuits, controller circuits and interface circuits. In some examples, some of these circuits are not formed in the peripheral area but are formed on a separate chip. Thus, peripheral circuits may be different from one memory chip to another. Any circuit that is fabricated on the same chip as a memory array but is not a part of the memory array may be considered to be a peripheral circuit. The area of such a chip that is outside the memory array may be considered the peripheral area. Peripheral circuits may be very different from circuits of the memory array. For example, larger devices with thicker gate dielectric may be present in the peripheral area in order to handle high voltages. The differences between the memory array and peripheral area may cause problems with certain process steps.
One process step that may produce different results in the memory array and peripheral area is Chemical Mechanical Polishing (CMP). CMP may be used to planarize a surface of a substrate by polishing the surface against an abrasive pad with a chemical slurry between the surface and the pad. Typically, prior to CMP the surface is uneven because of deposition or removal of one or more layers of material. In principle, CMP removes material across the wafer surface in a manner that leaves a planar surface. In reality, local features may cause the surface to be non-planar. For example, a depression in a surface prior to CMP may remain to some extent after CMP. Such “dishing” is the result of removal of material at the bottom of the depression where the depression is wide enough to allow CMP action at the bottom of the depression. Dishing tends only to occur for larger depressions so that it may not affect a memory array but may be significant for a peripheral area having large features. Previous approaches to the problem of dishing include forming dummy patterns in the area where dishing is likely to occur so that there is more material to remove in this area. However, forming dummy patterns generally involves an extra patterning step to establish the locations of the dummy patterns.
Thus, there is a need for a method of forming a memory array with low aspect ratio STI structures and a high coupling ratio between floating gates and control gates. There is also a need for a method of forming a memory array that has a high degree of control of the coupling between floating gates and control gates so that the coupling ratio is uniform. There is also a need for a method of forming a memory array on a memory chip having peripheral circuits where planarization is achieved across both the memory array and the peripheral circuits.